(1) Field of the Invention
The present invention relates to a reception pointer processing apparatus in SDH transmission system, especially a reception pointer processing apparatus used advantageously for the synchronized optical communication network called SONET in the North America.
(2) Description of the Related Art
As it is well-known, in recent optical transmission technology, following the standardization by ITU-T, a transmission unit based on a synchronous transmission system called an SDH (Synchronous Digital Hierarchy) [transmission system based on a synchronous transmission system called an SONET (Synchronous Optical Network) in the North America] is mainly developed in place of a transmission system based on the general asynchronous transmission system called a PDH (Presiochronous Digital Hierarchy).
Moreover, recently, as the circuit capacity (transmission rate) processed by these SDH transmission apparatus or SONET transmission apparatus is increased significantly for instance from 600 Mbps to 10 Gbps, respective transmission apparatus are needed to be increased in capacity and in rate.
FIG. 29 shows an example of a representative SONET (SDH) transmission network. The example shown in FIG. 29 is called PPS (Path Protection Switched) ring network and comprises a plurality of multiplexing apparatus 101 to 106 (node A to F) connected in ring, wherein a multiplexed frame (transmission frame) called STS (Synchronous Transport Signal) in SONET and STM (Synchronous Transfer Mode) in SDH is so composed to communicate all the way switching over Primary/Secondary path depending on the state of the transmission line among respective multiplexing apparatus.
Here, among the respective multiplexing apparatus 101 to 106, multiplexing apparatus 101, 103, 104 and 106 (nodes A, C, D and F) are respectively designed mainly for relaying input transmission frame and various processings will be performed including the replacement processing of an overhead for this multiplexed frame, the pointer replacement processing and others.
On the other hand, the remaining multiplexing apparatus 102 and 105 (nodes B and E) perform respectively overhead termination processing for the multiplexed frame and send to the terminal side, by extracting the lower order group signal [for instance, VT (Virtual Tributary)1.5, DS1 (Digital Signal level 1) and others], containing in the frame or compose a multiplexed frame by adding the overhead through the multiplexing of the lower order group signal from the terminal side.
In the above composition, the SONET transmission network (PPS ring) shown in this FIG. 29 allows to transmit data (transmission frame) with a high rate all the way conserving an extremely high maintenance and operation capability by relaying or terminating STS frames in multiplexing apparatus 101 to 106 and, at the same time, by transmitting all the way switching over the path to be used (primary/secondary path) conveniently.
The overhead in the SONET (SDH) transmission system is classified into a section overhead (SOH) for transmission line and a path overhead (POH) for path and in the multiplexing process, a method is employed to multiplex by adding the path overhead (POH) to a signal of the lower order group side and by adding the section overhead (SOH) at last.
In the SONET (SDH), at this time, the information (pointer) indicating the frame leading position or the frame composition of respective lower order group signals contained in the multiplexed frame will be indicated in a portion called a pointer byte in the overhead so as to permit to perform the relay or termination processing in the multiplexed frame while adjusting the slight frequency (phase) displacement of lower order group signals contained in the multiplexed frame.
So it becomes very important to process the pointer on data (multiplexed frame) transmission in the SONET (SDH) transmission system.
FIG. 30 is a block diagram showing a composition of essential parts of the multiplexing apparatus 10i (provided that i=1 to 6) in respect of the pointer processing function. In the multiplexing apparatus 10i shown in this FIG. 30, the STS-12 frame after overhead termination processing is received as 8 serial data (78 Mbps) and the pointer processing for this frame (reception/transmission pointer processing) is performed in parallel by the STS-1 frame unit and the apparatus comprises, as shown in FIG. 30, a separation section (DMUX) 111, a reception pointer processing section 112-1 to 112-12, a clock changeover section (ES section) 113-1 to 113-12, a transmission pointer processing section 114-1 to 114-12, a multiplexing section (MUX) 115, an alarm processing section 116 and a PAIS transmission control section 117.
Here, the separation section 111 changes the rate of input data (8 serial data) into the 96 parallel data [S/P (serial/parallel) conversion: 78 Mbps-&gt;6Mbps] to separate into the STS-1 frame of 12 channels; the reception pointer processing section 112-j (provided that j=1 to 12) is designed to perform respectively the reception pointer processing as shown in the following items (1) to (3) for instance in respect of the STS-1 frame [channel data (ch. j)] in its charge and here, the pointer processing will be performed based on the state transition corresponding to the leading channel and the dependent channel individually for each channel according to the frame size (kind) setting [concatenation (CONC) setting: STS-3c/12c] established fixedly from the outside.
(1) Generation of J1 enable signal by detecting the leading position (J1 byte position) of the lower order group signal contained in the channel data from pointer byte (H1, H2 byte; total 16 bits) contained in a data channel. PA1 (2) Detection of the NDF (New Data Flag)-bit, the SS-bit and the 10-bit pointer value of the pointer byte. PA1 (3) Alarm detection of the PAIS (Path Alarm Indication Signal), the LOP (Loss Of Pointer) or the like from the pointer byte.
Here, the NDF-bit is the bit comprising 4 bits to be used for changing immediately the operation pointer value (active pointer value) to a new pointer value and 3 bits or more should correspond with "1001" as the detection condition of NDF enable.
The SS-bit is, on the other hand, the bits (2 bits) used for indicating the frame size of the lower order group signal contained, while 10-bit pointer value is the bits used for indicating in binary code the leading position (offset pointer value) of the contained lower order group signal and they comprise respectively 5 bits increment-bit (I) and decrement-bit (D).
Moreover, the PAIS will be detected when all pointer bytes are "1" and the LOP is detected when invalid pointer is detected sequentially for given number of times (8 times for instance) and, when these anomalies are detected, the PAIS transmission control to the transmission pointer processing section 114-j will be performed by the PAIS transmission control section 117 in order to inform the downstream devices of the transmission date as the AIS state.
The clock changeover section 113-j is designed for clock changing [transmission line.fwdarw.system side clock changeover] the channel data (main signal data) after reception pointer processing in the corresponding reception pointer processing section 112-j respectively while the transmission pointer processing section 114-j is composed to detect NDF enable or to detect staff request, or to detect transmission pointer value for the main signal data after clock changeover processing in the corresponding ES section 113-j respectively.
The multiplexing section 115 is designed to rate-convert (P/S conversion) the main signal (96 parallel data) processed in parallel by the STS-1 unit in the reception pointer processing section 112-j, the ES section 113-j and the transmission pointer processing section 114-j into original 8 serial data before outputting it while the alarm processing section 116 performs the alarm processing corresponding to the frame kind (CONC) setting (STS-1/3c/12c) from outside, based on the PAIS, the LOP transition information detected by respective channel units as mentioned below in the reception pointer processing section 112-j.
The PAIS transmission control section 117 outputs the PAIS transmission control signal when the PAIS or the LOP is detected by the channel unit in the reception pointer processing section 112-j and outputs compulsorily the PAIS transmission control signal to all channels independently of the state of the reception pointer processing section 112-j (PAIS, LOP) upon reception of the higher order group alarm [LOS (Loss Of Signal), LOF (Loss Of Flame), MS (Multiplexing Section) AIS or the like] detected at the reception end on the transmission line frame.
In the multiplexing apparatus 10i composed as mentioned above, first, the input data is separated into the channel data of the STS-1 unit through 8.fwdarw.96 S/P conversion in the separation section 111. Separated data of 12 channels is submitted to the detection of alarm (LOP, PAIS) or the pointer value by the channel data (STS-1) in the reception pointer processing section 112-j before being transmitted as the main signal data (main signal, J1 enable signal) to the clock changeover section 113-j.
In the clock changeover section 113-j, the clock changeover of the main signal and the J1 enable signal input from the reception pointer processing section 112-j to line.fwdarw.system side is processed in parallel for 12 channels by the STS-1 unit and the main signal data after the clock changeover is transmitted to the transmission pointer processing section 114-j.
In the transmission pointer processing section 114-j, the detection of the NDF enable request, the detection of the staff request or the detection transmission pointer value are respectively executed in parallel for 12 channels, by the STS-1 unit, from the main signal data after the clock changeover in the clock changeover section 113-j to insert the pointer byte (H1, H2 byte).
Here, when the PAIS, the LOP at the reception pointer processing section 112-j or LOS, LOF, MS-AIS or other higher order group alarms at the transmission frame reception end are detected, under the control of the PAIS transmission control section 177, the main signal data will all be set to "1".
Then data processed in parallel by the STS-1 unit respectively in the reception pointer processing section 112-j, the clock changeover section 113-j and the transmission pointer processing section 114-j as mentioned before is submitted to 96.fwdarw.8 P/S conversion (6 Mbps.fwdarw.78 Mbps) in the multiplexing apparatus 115 before the transmission.
In other words, the multiplexing apparatus 10i is so composed to separate the STS-N (N=48, 192, . . . ) level multiplexed frame of the STS-12 level or more into the STS-1 frame, minimum path unit for executing in parallel respective reception pointer processings and transmission pointer processings.
To be specific, the reception pointer processing section 112-j (reception pointer processing apparatus) comprises, as shown respectively in FIG. 30, the H1/H2 byte detection section 118, the pointer detection section 119 and the pointer value updating section 120 while the pointer detection section 119 comprises the PAIS detection section 121, the LOP detection section 122, the concatenation (CONC) detection section 123, the NDF enable detection section 124, the normal pointer 3-consecutive agreement detection section 125, the staff detection section 126 and the alarm detection section 127.
Here, the H1/H2 byte detection section 118 detects (latches) the pointer byte (H1 and H2 bytes: 16 bits) corresponding to the concerned channel from the main signal input data (channel data), in the pointer detection section 119, the PAIS detection section 121 detects the PAIS from the H1 and H2 bytes detected in the H1/H2 byte detection section 118, the LOP detection section 122 detects the LOP from the H1 and H2 bytes while the CONC detection section 123 detects concatenation indication (CI) indicating that the input channel data is in the concatenation state (called sometimes "concatenation" hereinafter) such as STS-3c/12c from the H1 and H2 bytes.
On the other hand, the NDF enable detection section 124 detects the NDF enable from the H1 and H2 bytes, the normal pointer 3-consecutive agreement detection section 125 detects reception of the 3-consecutive normal pointers of the same value from the H1 and H2 bytes while the staff detection section 126 detects staff information (INC/DEC) from the H1 and H2 bytes.
Moreover, the pointer value updating section 120 performs the updating processing of the active pointer value based on the results of respective detections in the CONC detection section 123, the NDF enable detection section 124, the normal pointer 3-consecutive agreement detection section 125 and the staff detection section 126 while the alarm detection section 127 detects the alarm information (transition information to PAIS state, LOP state) by the STS-1 unit based on the respective detection result of respective detection sections 122 to 125.
More particularly, the pointer detection section 119 is composed for example as shown in FIG. 31. In this FIGS. 31, 128 is a NDF-bit monitoring section for monitoring NDF-bit (No. 1 to 4 bit in a pointer byte) for performing the detection of all "1", detection of "1001" and detection of agreement of 3 or more bits with "1001" while 129 is an SS-bit monitoring section for monitoring SS-bit (No. 5 and 6 bit in a pointer byte) to detect all "1" and to monitor the SS-bit normal reception.
130 is a 10-bit pointer monitoring section for monitoring 10-bit pointer value (No. 7 to 16 bit in a pointer byte) to detect all "1", to monitor "000" to "782" (Offset Value in Range), range showing the normal path accommodation (containing) position and to monitor the comparison result with active pointer value up to the previous frame and I-bit, D-bit for the staff detection respectively.
131 is an AND gate composing the PAIS detection section 121 shown in FIG. 30 with the respective monitoring sections 128 to 130, is designed to output the PAIS indication when respective output becomes all "1" and the pointer byte all "1" by executing logical product of output from respective monitoring sections 128 to 130.
132 is an AND gate composing the CONC detection section 123 with respective monitoring sections 128 to 130, is designed to output the concatenation indication signal when the NDF-bit is "1000", SS-bit normal reception and 10-bit pointer value is all "1" by executing logical product of output from respective monitoring sections 128 to 130.
133 is an AND gate composing the NDF enable detection section 124 with respective monitoring sections 128 to 130, is designed to output the NDF enable signal when the NDF-bit agrees with "1001" for 3 bits or more, SS-bit normal reception and 10-bit pointer value is within the range indicating a normal path containing position ("000" to "782") by executing logical product of output from respective monitoring sections 128 to 130.
134 is one input inversion type AND gate composing the normal pointer 3-consecutive agreement detection section 125 with respective monitoring sections 128 to 130, is designed to output respectively "H" pulse when the NDF-bit is other than agreement with "1001" for 3 bits or more, SS-bit normal reception and 10-bit pointer value indicates a normal path containing position, while it outputs normal pointer 3-consecutive agreement signal when this "H" pulse input for the 3-consecutive frame into a 3-stage protection section 138 mentioned below.
135 is a staff information detection section composing the staff detection section 126 with respective monitoring sections 128 to 130, and is designed to detect INC/DEC staff information in response to I-bit/D-bit inversion number of 10-bit pointer value.
On the other hand, 136 to 139 are respectively the 3-stage protection sections and, here, 136 is used for the 3-frame consecutive reception protection of the PAIS indication, 137 for the 3-frame consecutive reception protection of the concatenation indication, 138 for the 3-frame consecutive reception protection of the normal pointer indication and 139 for the 3-frame staff operation inhibition protection after the staff operation [frame containing position shifting (.+-.1)] respectively.
More particularly, the respective 3-stage protection section 136 to 139 is composed, as shown in FIG. 32 for example, two FF circuits 152, 153 and a 3-input AND gate 154 and the output (protected output) from the AND gate 154 becomes "H" when FF circuits 152, 153 operate by 1 frame and detection pulse (any of PAIS indication, CONC indication, normal pointer indication or staff indication) is input for 3-consecutive frames.
In FIGS. 31, 140 and 141 are respectively NOR gates for detecting invalid pointer indicating invalid pointer indication on a pointer byte; NOR gate 140 detects invalid pointer for channels corresponding to the dependent channel at the moment of the CONC setting, and takes the state other than PAIS indication and concatenation indication as invalid pointer. While the NOR gate 141 detects the invalid pointer for channels corresponding to the leading channel at the moment of the CONC setting, and takes the state other than the PAIS indication, the normal pointer indication and the staff indication (INC/DEC) as invalid pointer.
Moreover, 142 is a selector for detecting the invalid pointer of each leading/dependent channel by changing over the output from the respective NOR gates 140, 141 by the CONC setting which is the external input. Here, this FIG. 31 represents a dependent (CONC) channel setting when the CONC setting signal is "H".
144, 145 are 8-stage protection sections for detecting respectively the LOP state (transition condition); 8-stage protection section 144 detects the 8-consecutive invalid pointer while the 8-stage protection section 145 detects the 8-consecutive receptions of the NDF enable (monitoring only NDF-bit) respectively. Here, when the leading channel is set, the logical sum result by OR gate 146 of invalid pointer 8-stage protection and NDF enable reception 8-stage protection is taken as the LOP transition condition, while when the dependent channel is set, as the NDF enable reception 8-stage protection is unnecessary, "L" fixed output is realized by the CONC setting signal to the selector 143.
147 is also a selector for selecting the normal pointer reception condition which is the transition condition from the PAIS or LOP state to the normal (NORM) state, and as transition condition to NORM state is different in the leading channel setting and the dependent channel setting, it is designed to select the detection of NORM.times.3 in the leading channel setting and the detection of CONC.times.3 as normal pointer reception condition in the dependent channel setting.
148 is a 3-input OR gate for detecting the transition (cancel) condition from the PAIS state to the NORM (CONC) state or the LOP state by the logical sum of NORM (CONC).times.3, NDF enable and LOP, while 149 is a 2-input OR gate for detecting the transition (cancel) condition from the LOP state to the NORM (CONC) state or the PAIS state.
On the other hand, 150, 151 are respectively JK-FF (J-K flip-flop) circuits for determining respective reception state of the PAIS, LOP from PAIS transition condition of output from the 3-stage protection section 136, LOP transition condition of output from 8-stage protection section 144, 145 and detection output of respective state cancel condition of output from OR gate 148, 149.
In the above composition, this pointer detection section 190 may perform accurately respective detection processings of the NDF enable, the normal pointer 3-consecutive agreement reception, the PAIS state, the LOP state or the like for the channel data in its charge by monitoring (detecting) the NDF-bit, the SS-bit and the 10-bit pointer value contained in the input transmission frame pointer byte.
Now, FIG. 33 is a block diagram showing an example of the pointer value updating section 120 shown in FIG. 30. As shown in this FIG. 33, the pointer value updating section 120 comprises a frame counter 154, an offset counter (783-ary counter) 155, a J1 counter (783-ary counter) 156, a selector 157, 164, a latch section 158, a comparison section 159, a decoder 160, an AND gate 161, an enable control section 162 and updating timing generation section 163.
Here, the offset counter 155 is designed to count the input data bit number in synchronous operation with the input data frame pulse, the offset counter 155 counts the bit number of SPE data [pointer offset number ("000" to "782")] in the STS-1 frame while the J1 counter 156 counts 783 bits from the previous frame containing the leading position (J1 enable) for counting the J1 pulse position which is to be the leading position of the next frame. Note that these respective counters 155, 156 are controlled by the frame counter 154.
The selector 157 selects the reception pointer value and the counter value of the offset counter 155 to output as the active pointer value, while the latch section 158 latches the active pointer value from this selector 157. The comparison section 159 compares the offset counter 155 counter value and the active pointer value latched by the latch section 158 to output the J1 pulse if respective values agree.
Moreover, the decoder 160 decodes "782" of the active pointer value while the AND gate 161 takes logical product of offset counter 155 output, the decoder 160 output and the INC indication detected by the staff information detection section 135 shown in FIG. 31 to send the active pointer value updating ("782".fwdarw."000") instruction to the updating timing generation section 163 upon the reception of the INC indication when the active pointer value is "782".
On the other hand, the enable control section 162 executes the enable control for the J1 counter 156 for performing ".+-.1" phase control for the J1 pulse output position of the previous frame upon the reception of INC/DEC (staff indication) while the updating timing generation section 163 controls the writing (updating timing) of the active pointer value into the latch section 158 to write the reception pointer value into the latch section 158 as the active pointer value by respective detection timings upon the 3-frame consecutive reception of the NDF enable, the normal pointer indication while, upon the reception of INC/DEC indication, by the J1 pulse timing from the J1 counter, the offset counter 155 counter value is written into as the active pointer value.
The selector 164 selects the active pointer value from the comparison section 159 and the J1 pulse from the J1 counter 156, and is designed to select the J1 pulse from the J1 counter 156 upon the reception of staff indication (INC/DEC) and to select the active pointer value from the comparison section 159 for other cases.
By the composition mentioned before, in this pointer value updating section 120, upon the 3-frame consecutive reception of the NDF enable, the normal pointer indication, the reception pointer value is written into the latch section 158 as the active pointer value by the respective reception (detection) timing, while upon the reception of INC/DEC indication, the offset counter 155 counter value is written into the latch section 158 as the active pointer value according to the J1 pulse timing generated by the J1 counter 156 so as to allow constantly a correct active pointer value updating even when the INC/DEC staff indication is received.
However, the reception pointer processing section 112-j (reception pointer processing apparatus) is deprived of a function for automatically judging which is the frame composition (frame size) of the reception data (STS-12 frame) among the STS-1/3c/12c but the reception pointer processing is executed corresponding to the concerned concatenation setting by a fixed frame size setting (concatenation setting) from outside so as to disable the correct reception pointer processing if data other than the set frame size is entered.
Moreover, in the reception pointer processing apparatus, the transmission frame where a plurality of channel data (STS-1 frame) is multiplied is separated for each channel by the separation section 111 before parallel reception pointer processing at STS-1 level bit rate by respective reception pointer processing section 112-j so as to require processing circuit corresponding to the number of channels (12 channels for STS-12) increasing substantially both the apparatus size and the power consumption.